Apparatus and method for a digital delay locked loop

ABSTRACT

A circuit and method is shown for digital control of delay lines in a delay locked loop (DLL) system. A pair of multiplexors (MUXes) is used to select output taps from a pair of complementary delay lines that delay a reference clock signal in order to lock onto a received clock signal. An output tap from one delay line is used to produce a rising edge in an output clock signal while a corresponding tap in the complementary delay line is used to produce a falling edge in the output signal in order to correct for distortion. The MUXes are controlled based on a phase difference detected between the received clock signal and a feedback clock corresponding to the output clock signal. Another aspect of the present invention provides for generation of a quadrature clock by interpolating between the rising and falling edges selected for the output clock signal. Still another aspect of the present invention provides for selectively disabling unused elements of the delay lines to reduce power consumption.

FIELD OF THE INVENTION

[0001] This present invention relates to digital circuits. Morespecifically, it relates to delay locked loop design.

BACKGROUND OF THE INVENTION

[0002] Accurate high-speed clock signals are often used for transmittingand receiving data in high-speed circuits, such as high-speed memorydevices or high speed bus channels. However, high speed clock signalsoften become distorted during transmission and reception. Consequently,high speed circuits, such as dynamic random access memory (DRAM)devices, often recover an externally provided high-speed clock signal bylocking an accurate internally generated clock signal to the distortedexternally provided clock signal.

[0003] A delayed locked loop (DLL) is typically used to delay theinternally generated clock signal in order to match the phase of theinternally generated clock signal to the phase of some reference clocksignal. Typically, a phase-detection circuit in the DLL compares thephase of the internal clock signal to the reference signal and acontrol-logic block that is coupled to the output of the phase-detectioncircuit is used to increase or decrease a delay produced by a chain ofdelay elements used to delay the internal clock signal. U.S. Pat. Nos.5,945,862 and 6,125,157 to Donnelly et al. represent two approaches tolocking an internal clock signal to an external clock signal using delayelements.

[0004] It is desirable to provide for a fully digital DLL circuit thatcan be fabricated using standard digital design techniques.

SUMMARY OF THE INVENTION

[0005] In accordance with a first aspect of the present invention, acircuit for selectively delaying a reference clock signal is provided.The circuit includes a phase splitter coupled to a first delay line anda second delay line. Each delay line includes a set of output taps andhas a multiplexor that is selectively coupled to the output taps. Anoutput of each multiplexor is coupled to a latch. The latch provides anoutput clock signal, which may be fed back to a phase detector, wherethe phase detector also receives an input clock signal. A controller iscoupled to the phase detector and, depending upon the output of thephase detector, provides control signals to each multiplexor.

[0006] In a preferred embodiment, the circuit is implemented usingstandard digital design techniques.

[0007] In accordance with a second aspect of the present invention, amethod for recovering a clock signal from an input clock signal isprovided. The method includes converting a reference clock signal intoan in-phase reference and a complementary reference, and selectivelydelaying the in-phase reference and the complementary reference. Themethod further includes generating an output clock signal from theselected in-phase reference and the selected complementary reference.

[0008] In accordance with the preferred embodiment, the selective delayof the in-phase reference and the complementary reference is based upona difference signal determined by comparing an input clock signal with afeedback clock signal, where the feedback clock signal is related to theoutput clock signal.

[0009] In accordance with another embodiment, the method is implementedusing digital design techniques.

[0010] This summary is not intended to be all-inclusive, but ratherillustrative. These and other aspects of the present invention, and itsvarious embodiments, are described in greater detail below.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Preferred embodiments of the present inventions are describedwith reference to the following drawings, wherein:

[0012]FIG. 1 is a functional block diagram of one embodiment of a DLLcircuit according to the present invention;

[0013]FIG. 2 is a timing diagram illustrating an example of the functionof the DLL circuit of FIG. 1;

[0014]FIG. 3 is a control flow diagram illustrating an embodiment of thefunction performed by the controller of FIG. 1;

[0015]FIG. 4 is a logic circuit diagram illustrating an embodiment of acircuit for generating a quadrature clock according to one aspect of thepresent invention;

[0016]FIG. 5 is a control flow diagram illustrating an embodiment of thefunction performed by a controller to generate control signals to obtainthe quadrature clock signal from the circuit of FIG. 4;

[0017]FIG. 6 is a timing diagram illustrating an example of the functionof the quadrature clock circuit of FIG. 4;

[0018]FIG. 7 is a functional block diagram of another embodiment of aDLL circuit according to the present invention;

[0019]FIG. 8 is a functional block diagram illustrating an example of adelay element suitable for use in the delay line circuits of FIG. 7;

[0020]FIG. 9 is a control flow diagram illustrating an embodiment of thefunction performed by the controller of FIG. 7;

[0021]FIG. 10 is a functional block diagram illustrating an example of acircuit for detecting a cycle boundary in the delay line circuits ofFIG. 7;

[0022]FIG. 11 is a transistor circuit diagram which illustrates anexample of a prior-art tri-state inverter circuit configured to beenabled by a differential enable signal that may cause a multiplexorcircuit which uses it to experience a data dependent response;

[0023]FIG. 12 illustrates a circuit that addresses the problem of datadependent response exhibited by the circuit of FIG. 11;

[0024]FIG. 13 is a functional block diagram illustrating an example of atwo level multiplexor design suitable for use with the circuits of FIG.1 and FIG. 7; and

[0025]FIG. 14 is a logic circuit diagram illustrating an embodiment of aRS flip-flop suitable for use in the described embodiments.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0026] In one preferred embodiment, a reference clock having a correctduty cycle, e.g. 50%, is split into an in-phase clock reference signaland a complementary reference clock signal, each of which issuccessively delayed using a pair of delay lines. A set of output tapson the delay line allows the selection of and variation in the length ofthe delay. A pair of multiplexors (MUXes) is used to select one outputtap from each of the delay lines. In accordance with one preferredembodiment, a rising edge of a signal from the output tap selected fromthe delay line used to delay the in-phase reference signal is used toproduce a rising edge in an output clock signal. Then, a rising edge ofa signal from the output tap selected from the delay line used to delaythe complementary reference signal is used to produce a falling edge inthe output clock signal. A feedback clock signal is compared to theinput clock signal in order to obtain a difference signal that reflectsthe phase relationship between the feedback clock signal and the inputclock signal. A control circuit monitors the difference signal andgenerates a control signal that drives the selection performed by theMUXes such that a rising edge of the feedback clock is aligned orlock-in to a rising edge of the input clock signal.

[0027] In another aspect of the preferred embodiment, a power controlsignal controls delay elements within the delay lines and the controlcircuit is configured to generate the power control signal based uponthe control-signal provided to the MUXes such that unused elements inthe delay lines are disabled during operation to reduce powerconsumption.

[0028] In still another aspect of the present invention, four additionalMUXes are used to select output taps from each of the delay lines inorder to produce a quadrature clock signal. The additional outputs tapsare selected such that they are offset from the previously selectedoutput taps by an offset value, where one offset output tap is advancedby the offset value and the other offset output tap is delayed by theoffset value. The additional output taps are interpolated in order togenerate the quadrature clock. A quadrature control circuit varies theoffset value and monitors the relationship between edges in the signalsfrom the offset output taps in order to drive the additional pairs ofMUXes. The quadrature control circuit selects an offset value thatresults in the edges from the offset output taps being generallyaligned.

[0029]FIG. 1 is a functional block diagram of one embodiment of a delaylocked loop (“DLL”) circuit according to the present invention. Areference clock signal REFCLK is received by a phase splitter 102, whichsplits the REFCLK into a positive phase reference signal RP (alsoreferred to as an in-phase reference signal) and a negative phasereference signal RN that is 180° out of phase with RP (also referred toas the complementary reference signal). The positive phase reference RPis input to a delay line 110, which has N output taps that are input toa multiplexor (MUX) 112. The MUX 112 also receives a CONTROL signal thatselects one of the N inputs from the delay line 110 to be output fromthe MUX 112 as a ZUP signal to set an S input of a Set/Reset latch 130.The delay line 110 successively delays the reference signal RP such thateach one of the N output taps represents RP delayed by a multiple of apredetermined delay interval. Thus, selecting one of the N output tapsfrom the delay line 110 using the MUX 112 permits the RP signal to bedelayed by from 1 to N delay intervals before being input to the Sterminal of the latch 130.

[0030] Likewise, the delay line 120 delays the negative phase referencesignal RN by from 1 to N delay intervals, as selected by the MUX 122.The delay line 120 receives RN and has N output taps that are input tothe MUX 122. The MUX 122 also receives the CONTROL signal, whichdetermines which of the N output taps of the delay line 120 to output asa ZDOWN signal to a reset input R of the latch 130. The MUX 122 isconfigured to respond to the CONTROL signal in the same fashion to theresponse of the MUX 112. In other words, the delay line 120 and the MUX122 are configured relative to the delay line 110 and the MUX 112 suchthat the ZUP and ZDOWN signals are complementary to one another ingenerating signals responsive to the CONTROL signal output by controller140. The ZUP and ZDOWN signals control the up/down edges of the outputsignal. The output signal drives some collection of circuitry to producea signal FB_CLK that is aligned in zero degrees in phase with the inputclock signal. The resulting output clock signal CLKOUT generated bylatch 130 is a clock signal whose edges are determined by the CONTROLsignal and which has a 50% duty cycle.

[0031] A phase detector circuit 142 receives a feedback clock signalFB_CLK derived from the CLKOUT signal and also receives an input clocksignal INPUT CLK that is the signal to which the circuit 100 is to lockonto. The CLK_OUT may move in time in a manner that the resulting phaserelationship of the FB_CLK relative to the INPUT CLK is well managed.

[0032] The phase detector 142 compares the FB_CLK and the INPUT CLK andoutputs a difference signal DIFF that indicates whether the phase ofFB_CLK leads or lags the phase of INPUT CLK. The DIFF signal is receivedby the controller 140, which adjusts the CONTROL signal accordingly. Asone example for the control circuit 140, the circuit may consist of acounter, which is incremented or decremented by the DIFF signal in orderto adjust the CONTROL signal. It should be understood that someoneskilled in art of PLL or DLL design will recognize that the circuitwhich provides the control signal to the VCO or delay-line of a DLL canbe implemented in many fashions, and other circuits of varyingcomplexity could also be used.

[0033]FIG. 2 is a timing diagram illustrating an example of the functionof the DLL circuit of FIG. 1. In FIG. 2, the reference clock signalREFCLK is shown along with the reference clock signals RP and RN outputfrom the phase splitter 102. Note that REFCLK has a 50% duty cycle. Alsonote that RP and RN are complementary to one another, e.g. 180°out-of-phase with one another and that a delay is introduced to RP andRN relative to REFCLK by the phase splitter 102.

[0034]FIG. 2 also includes an example of an external input clock signalINPUT CLK. Note that, in this example, the INPUT CLK signal waveform isdistorted due to the effects of transmission and, consequently, thereceived INPUT CLK waveform does not have a 50% duty cycle. In oneembodiment, phase detector 142 compares the phase of rising edge 150 ofINPUT CLK to the FB CLK, which is derived from CLK OUT. Controller 140receives the DIFF signal and adjusts the value of the CONTROL signal inorder to select a delay tap DP(n) from delay line 110 that aligns therising edge of FB CLK with the rising edge 150 of INPUT CLK. In thisexample, DP(n) is selected such that rising edge 152 of DP(n) is alignedwith rising edge 150 of INPUT CLK. The rising edge 152 of DP(n), inturn, drives the set input of the latch 130 triggering the rising edge154 of the CLK OUT signal.

[0035] The CONTROL signal will also select DN(n), from the delay line120, for output by the MUX 122 to the reset terminal of the latch 130.DP(n) and DN(n) are generally complementary to one another, but aretypically distorted by their respective delay lines 110 and 120 suchthat neither DP(n) nor DN(n) will have a correct 50% duty cycle.However, the distortion will effect the rising edges of DP(n) and DN(n)in the same manner. Therefore, while the duty cycles of DP(n) and DN(n)are distorted, the relationship between the rising edge 152 of DP(n) andthe rising edge 160 of DN(n) is reliable. Thus, in the presentinvention, rising edge 160 of DN(n) is used to drive the reset input ofthe latch 130 triggering a falling edge 162 of the CLK OUT. The cyclethen continues as demonstrated by next subsequent a rising edge 170 ofDP(n) that triggers a rising edge 172 of the CLK OUT. The result is thatthe circuit 100 of FIG. 1 may produce a CLK OUT signal having a 50.%duty cycle.

[0036] Note that the timing diagram of FIG. 2 has been simplified todemonstrate the relationship between edges in the various waveforms. Theactual waveforms are subject to further delays introduced, for example,by the MUXes 112 and 122, the latch 130, as well as other circuitry thatis intermediate to the CLK OUT signal and the FB CLK signal.

[0037] As noted above, the controller 140 may be, for example, acounter, or composed of complex circuitry, such as a processor, thatmonitors the output of the phase detector 142 and generates the CONTROLsignal. FIG. 3 is a control flow diagram illustrating an embodiment of aprocess 180 performed by the controller 140 for generating the CONTROLsignal. In the process 180, at step 182, an initial value of n isselected and, at step 184, the CONTROL signal for controlling the delayof delay lines 110 and 120 is generated according to the initial valueof n selected at step 182.

[0038] At step 186, the output of the phase detector 142 is checked todetermine if signal lock has been achieved between FB CLK and INPUT CLK,e.g. the rising edge of FB CLK is aligned with the rising edge of INPUTCLK. If signal lock is achieved, then control flow branches at step 190to step 194, where the process waits for a short time interval beforebranching back to step 186 to check the output of the phase detector 182again.

[0039] If signal lock is not achieved, then control flow branches atstep 190 to step 192 where the value of n is adjusted according to thephase detector output. For example, if the DIFF signal is negative, thenn is decremented. If the DIFF signal is positive, then n may beincremented. Process 180 then branches back to step 184, where theCONTROL signal is generated according to the adjusted value of n.

[0040] Note that other approaches are also possible. For example, thesignal lock branch step 190 and wait step 192 may be omitted so that thevalue of n is always adjusted. In this case, when signal lock isachieved, the value of the DIFF signal will toggle between positive andnegative on each loop through the process. Control for DLLs is wellunderstood in the art and one of ordinary skill will readily appreciatethat the circuit of FIG. 1 may be adapted to work with a variety ofapproaches to DLL design.

[0041] In another embodiment, a quadrature clock signal may also begenerated. A quadrature clock is a clock that is out-of-phase by 90° or270° from a main clock signal. FIG. 4 illustrates an embodiment of aquadrature clock generation circuit 200 that may be used in combinationwith the circuit of FIG. 1. The quadrature clock generation circuit 200includes a MUX 210 that receives N output tap lines of the delayedsignal DP from the delay line 110, and is controlled by a control signalXDPCTRL1, which selects one of the taps DP(n+X) for output to a firstinput of an interpolator circuit 262. The interpolator circuit 262illustrated in FIG. 4 is composed of three inverters 212, 220 and 232.Interpolator circuits are generally understood to those of ordinaryskill in the art, and other interpolator designs may be adapted for usein the present invention. The circuit 200 further includes a second MUX230, which receives the N output tap lines of the delayed signal DN fromthe delay line 120 and a control signal XDNCNTRL1, which selects one ofthe taps DN(n−X) for output to a second input of the interpolatorcircuit 262.

[0042] The interpolator circuit 262 interpolates between a rising edgeof the DP signal and the rising edge of the DN signal, i.e., it takes anaverage of the 0-degree signal and the 180-degree signal to generate a90-degree QUP signal. To do that, the interpolator 262 uses a lateversion of the DP signal and an early version of the DN signal, i.e.,the signals DP(n+X) and DN(n−X), respectively.

[0043] The inverter 212 of the interpolator circuit 262 receives theDP(n+X) signal, and the inverter 232 receives the DN(n−X) signal. Theoutputs of both inverters are coupled to the input inverter 220, whichpossesses a parasitic capacitance. The inverters 212 and 232 arerelatively small devices relative to the inverter 220. For instance, theinverter 200 may be twice the size of the inverters 212 and 232. Theinverters 212 and 232 will charge the parasitic capacitance of the inputof the inverter 220 until a threshold voltage for the inverter 220 isreached causing its output to change state in order to generate a QUPsignal to set an S input of an RS latch 260. When the signals drivingthe inverters 212 and 232 are separated in time by less than the time ittakes for the inverter 212 to fully transition the output of theinverter 220, then the inverter 232 contributes to the voltagetransition at the output of the inverter 220. Thus, the interpolatorcircuit 262 will interpolate between a late version of DP signal and anearly version of the DN signal in order to obtain a 90-degree QUPsignal.

[0044] Further, as illustrated in FIG. 4, the circuit 200 includes asecond pair of MUXs 244 and 246, and a second interpolator circuit 264composed of inverters 248, 250, and 252 that generate a 270-degree QDOWNsignal. The MUX 244 receives the N output tap lines of the delayed DPsignal from the delay line 110, and is controlled by a control signalXDPCNTRL2, which selects one of the taps DP(n−X) for output to thesecond interpolator circuit 264. Similarly, the MUX 246 receives the Noutput tap lines of the delayed signal DN from the delay line 120 andcontrol signal XDNCNTRL2, which selects one of the taps DN(x+N) foroutput to the interpolator circuit 264.

[0045] To generate the QDOWN signal, the interpolator circuit 264 takesan average of the 180-degree signal and the 0-degree signal (or360-degree signal) to generate a 270 degree QDOWN signal. To do that,the interpolator 264 uses an early version of the DP signal and a lateversion of the DN signal, i.e., the signals DP(n−X) and DN(n+X),respectively. The QDOWN signal is then input to a reset input R of thelatch 130, and the latch 130 outputs a quadrature clock Q_CLK_OUT thatis out-of-phase by 90 degrees or 270 degrees from the main clock.

[0046] The circuit 200 further includes a quadrature control circuit 240that generates the four control signals XDPCNTRL1, XDNCNTRL1, XDPCNTRL2,and XDNCNTRL2 that are input to the MUXes 210, 230, 244, and 246,respectively. The quadrature control circuit 240 receives a TEST signalalong with the value n from the CONTROL signal of the control circuit140 of FIG. 1 and uses the values of these signals to generate the fourcontrol signals for the MUXes. The value of the TEST signal qualifiesthe value of the offset signal X used by the quadrature control circuit240. As illustrated in FIG. 4, a phase detection circuit, such as a Dflip-flop 242, generates the TEST signal. The DP(n+X) signal selected atthe MUX 210 drives a data input terminal of the D flip-flop 242, whilethe DN(n−X) selected at the IUX 230 drives a clock input terminal of theD flip-flop 254. A Q output terminal of the flip-flop 254 generates theTEST signal for input to the quadrature control circuit 240.

[0047] According to one embodiment, starting with a small value of X andincrementing it, the flip-flop 242 will change the state from 1 to 0 atsome value of X that is used to generate the QUP and QDOWN signals.Similarly, a large value of X could be first selected and thendecremented until the transition occurs. Alternatively, the DN(n−X)signal could be input to the D input, and the DN(n+X) could be theninput to the clock input of the D flip-flop 242. In such an embodiment,the selected value of X corresponds to a value of X when the flip-flop242 changes from 0 to 1. Thus, the phase detection circuit detects whenthe first input is no longer ahead of the second input, at which pointthe step of incrementing/decrementing the value of X is stopped, and thevalue of X can be used as an input to the quadrature control circuit240.

[0048] The function of the interpolator of FIG. 4 is further explainedbelow in conjunction with FIG. 6.

[0049] In FIG. 4, a change in state of the TEST signal from the Q outputterminal of the flip-flop 242 indicates the midpoint between the twosignals being interpolated. FIG. 5 is a flow chart illustrating oneembodiment of a process 250 performed by the quadrature control circuit242. The process 250 starts from a minimum value for X, which isinitialized at step 252. The quadrature control circuit 240 thengenerates control signals at step 254 based upon DP(n+X) and DN(n−X),respectively. The functionality of the control circuit 240 may beintegrated with some embodiments of the control circuit 140 of FIG. 1.

[0050] The value of the TEST signal is checked at step 256 to determineif the TEST signal has transitioned from logic one to logic zero. If theTEST signal is at logic zero, then the midpoint may have not beenreached, and the control flow branches to step 262, where the value of Xis incremented. The control flow then branches back to step 254 where anew set of control signals is generated based on the incremented valueof X. The value of the TEST signal is again verified at step 256. If theTEST signal has transitioned to the logic zero, then the control flowbranches at step 260 to step 264, where the value of X is decremented.The value of X is decremented because the transition to logic zeroindicates that the midpoint has been passed and the value of X isdecremented, in this embodiment, to obtain a more accurate midpointvalue. The value of X is now set for operation, and the QUP and QDOWNsignals are generated. As mentioned in the preceding paragraphs, insteadof setting the value of X to a minimum value, the value of X may be setto a maximum value and then decremented until the transition isdetected.

[0051] Interpolation of the 90-degree quadrature clock signal isillustrated in the waveform of the timing diagram of FIG. 6. The edgesproduced by the DP(n+X) and the DN(n−X) are shown as the value of X issuccessively incremented (or decremented) until the two edges convergeat 90-degrees with the result being a QUP signal.

[0052] As noted above, a 270-degree clock signal may alternatively begenerated. Whereas the 90-degree QUP signal was derived by interpolatinga midpoint that is delayed from DP(n) and advanced from DN(n), e.g.,taking a late DP signal and an early DN signal, e.g., using DP(n+X) andDN(n−X), a 270-degree QDOWN signal can be derived from an early versionof DP signal and a late version of the DN signal, e.g., DP(n−X) andDN(n+X). The interpolation of the 270-degree QDOWN signal is alsoillustrated in the waveforms of the timing diagram of FIG. 6.

[0053] In accordance with another embodiment, unused delay elements ofthe delay lines may be powered down to save power. For example, once thevalue of n is determined, some or all of the subsequent delay elementsin the delay line may be turned off. FIG. 7 is a functional blockdiagram illustrating another embodiment of a DLL circuit 300 accordingto the present invention. The DLL circuit 300 of FIG. 7 is similar tothe DLL circuit 100 of FIG. 1, except that delay lines 310 and 320 arecomposed of delay elements that may be powered down and a controllercircuit 340 is adapted to generate a POWER CONTROL signal for poweringdown elements of the delay lines 310 and 320. In this embodiment, thecontroller 340 is obviously more complex than an up/down counter.

[0054]FIG. 8 illustrates one example of a delay element circuit 350 thatcan be powered down and is suitable for use in the delay lines 310 and320 of FIG. 7 and FIG. 1. The circuit 350 is a differential circuit thatreceives and outputs complementary signals. Inputs IN and INB receivethe delayed signal output from a previous delay element in a sequence oftie delay line. Outputs NEXT and NEXTB are output, for example, to thenext delay element in the sequence of the delay line. OUT and OUTB areoutput tap signals that are output to the MUXes 112 and 122. The delayfor the delay element circuit 350 is primarily provided by NAND gates360 and 362. Inverters 356 and 358 primarily help keep the delay passcomplimentarily. An ENABLE signal is input to each of the NAND gates 360and 362. When the ENABLE signal is at a logic one, then the input signalat input terminals IN and INB is enabled to pass through the delayelement to the next delay element and to the output terminals OUT andOUTB. When the ENABLE signal is at a logic zero, then the input signalat input terminals IN and INB is blocked. The NAND and inverter gatesmay be selected such that no current is drawn when no data transitionstake place, e.g. complementary metal-oxide semiconductor (CMOS) logic.

[0055] The POWER CONTROL signal output by the control circuit 340separately drives the ENABLE line of the delay elements in the delaylines 310 and 320. Once the value of n is determined to align the DLLcircuit with the INPUT CLK signal, then unused delay elements may bedisabled to reduce power consumption.

[0056]FIG. 9 is a control flow diagram illustrating an embodiment of aprocess 370 performed by control circuit 340 for determining the valueof n and setting the POWER CONTROL signal. Process 372 is similar toprocess 180 of FIG. 3. At step 372 (step 182 in FIG. 3) of process 370,the control circuit 340 initializes the value of n, and the POWERCONTROL signal is initialized such that all elements of delay lines 310and 320 are active. At step 374 (step 184 in FIG. 3), the delay CONTROLsignal is generated that drives the MUXes 112 and 122 of the delaycircuit 300 to select the output taps from the delay lines 310 and 320.At step 376 (step 186 in FIG. 3), the output from a phase detector ischecked to determine whether the phase of the FBCLK signal lags or leadsthe phase of the INPUT CLK signal. If the circuit 300 has not locked tothe INPUT CLK signal, then control flow branches at step 380 to step188, where the control circuit 340 adjusts the value of n according tothe signal output by the phase detector 142 and the control flow returnsto step 384 where the delay CONTROL signal is generated using the newvalue of n.

[0057] If the circuit 300 has locked onto the INPUT CLK signal, then thecontrol flow branches at step 380 to step 382, where the control circuit340 determines a power control position that may be used to adjust thePOWER CONTROL signal to turn off unused delay elements in the delaylines 310 and 320. At step 384, the control circuit 340 adjusts thepower control signal to turn off unused elements, and the adjustment isbased on the power control position determined at step 382.

[0058] According to an alternative embodiment, the N delay stages aheadof the maximum delay stage of interest may be powered-down. The powercontrol circuit monitors the ZLOOP and QLOOP delay line usage andapplies a power down signal to positions “MAX+N,” where “MAX” is thehighest position being used, and N is 1 and greater.

[0059] In a DLL circuit having a large delay line, an entire cycle ofthe reference clock frequency might be contained within the delay line.For instance, each step of a 64-bit delay line might be 50 pS, thus,producing a delay of 3.2 nS on the entire line. In such an embodiment,if the reference clock has a frequency of 500 MHz, the entire referenceclock cycle might be represented in 2.0 nS, or 40 stages, of that delayline, leaving 24 stages of the line unused. Therefore, it might beadvantageous to detect a cycle boundary, where a DLL circuit crossesover from a maximum delay value to a minimum delay value in locking ontoa signal.

[0060]FIG. 10 illustrates an example of a circuit 400 for detecting acycle boundary and generating a CYCLE BOUNDARY signal that may bereceived by a control circuit adapted, for example, to adjust theCONTROL signal to the MUXes 112 and 122 or the POWER CONTROL signalaccordingly. In the circuit 400, a delay line 410 having a series ofoutput taps receives the REFCLK signal. A first delay output tapDelay(0) is output to a MUX 412, and a maximum delay output tapDelay(N−1) is output to a MUX 414. An output of the MUX 412 drives abuffer 416 whose output is received by a phase detector 420. Likewise,an output of the MUX 414 drives a buffer 418 whose output is alsoreceived by the phase detector 420. An output of the phase detector 420is received by a reference control 430 that generates the CYCLE BOUNDARYsignal.

[0061] In one embodiment, the phase detector 420 receives a first outputof the delay line 410, a bit position (0), and finds another point onthe delay line 410 that matches the bit position (0) in phase. To dothat, the phase detector 420 may compare other bit positions, forexample sequentially and in order, until the phase detector 420 finds amatch. For instance, the phase detector 420 might check a position N todetermine if the bit position N is ahead or after the bit position (0),and, if it is not ahead, the phase detector 420 may instruct referencecontrol 430 to increment the bit position to N+1. At some point, if thereference frequency is fast enough, the phase detector 420 detects apoint where the bit position “N” happens before the bit position “0”. Atthat point, the phase detector 420 determines that one-cycle of thereference clock takes N stages of the delay line 410.

[0062] According to one embodiment, the cycle boundary number Ndetermined using the cycle boundary detector circuit 400 may be fed backto manage the primary loop circuit 140 described in reference to FIG. 1.During a normal operation, the circuit 140 may be arranged to incrementits bit position by one bit position every hour in order to track aslowly drifting reference signal. After some time, a loop may approach alast bit position, such as a bit position 64 of a 64-stage delay line,for instance. Instead of approaching the 64th stage of the delay line,at which point the loop becomes unlocked, and the data might be lostwhile the loop re-acquires, the loop might utilize the number Ndetermined by the cycle boundary detector circuit of FIG. 10. Using thevalue of N, the loop may determine that the bit position “64-N” may beconsidered as the bit position 64. Therefore, for instance, if N=40,instead of moving to position 64 on an “increment” step, the controllermay move to position 24. Alternatively, during an increment step, thecontroller may move to position “64-N+M”, where M is a fixed value, suchas 2, for instance.

[0063] Further, the value of “N” determined using the cycle boundarycircuit 400 may also be used by the quadrature loops. For example, if aquadrature loop (“Q-loop”) is locked at bit position 60, and the Q-loopcontroller is adapted to use +/−10 bit positions to create QUP and QDOWNsignals, the quadrature loop might require bit positions 50 and 70.However, in a 64-bit delay line, the Q-loop controller will not be ableto use the 70th bit position. However, if N=40, the Q-loop may use bitpositions 50 and 30.

[0064] One problem that can arise in a DLL is that the circuits used toimplement the MUX elements may have data dependent responsecharacteristics, e.g. the speed of the response to a logic zero isdifferent than the speed of the response to a logic one. FIG. 11illustrates an example of an inverter circuit 450 configured to beenabled by a differential enable signal that may experience a datadependent response. In the circuit 450, an enable signal EN, such as aline from the POWER CONTROL signal of the circuit 300 of FIG. 7, drivesan NMOS transistor 458 while a complementary enable signal ENB drives aPMOS transistor 452. When EN and ENB are active, then a DATA signal isinverted by a PMOS transistor 454 and an NMOS transistor 456 to drive anoutput terminal OUT. When EN and ENB are inactive, then the inverterformed by the transistors 454 and 456 is disabled because no current canflow between the power supply rails V_(DD) and V_(SS). The circuit 450suffers from data dependent behavior because the amount of capacitancethat the non-selected MUX paths contribute to the output node is afunction of the data signal driving the non-selected nodes. For example,if a first data input IN(0) is selected, the devices 454 and 456contribute one value of capacitance to the OUT node if the DATA(0) islow, and another capacitance value if DATA(0) is high. During theoperation, the propagation delay thru the MUX element from the selectedinput to the common output will therefore vary as a function of the datastates on the non-selected inputs, thus, resulting in a data dependentresponse.

[0065]FIG. 12 illustrates a circuit 470 that addresses the problem ofdata dependent response exhibited by the circuit of FIG. 11. In thecircuit 470, a first data input IN(0) is input to an inverter 472 whichdrives one input of a NAND gate 474. An output of the NAND gate 474drives an input of tri-state inverter 476. The output of the inverter476 is coupled to a common output circuit node OUT. A second input ofthe NAND gate 474 is driven by a first enable signal EN(0) derived fromthe CONTROL signal received by the MUX. The inverter 476 receives itstri-state control from EN(0). Each input to the MUX has a similarcircuit, as illustrated by the ellipses leading to gates 482, 484 and486 for processing Nth data input IN(N) and enable signal EN(N). Via thecircuit shown in FIG. 12, all of the non-selected MUX paths contributethe same amount of capacitance load to the output node, regardless ofthe data values on the non-selected paths. When EN(0) is low, the logicgate 474 blocks any contribution from IN(0) to the logic state at theinput of the tri-state inverter 476. If EN(0) is low, the logic gate 474drives the node at the input of the tri-state inverter 476 to a logichigh, removing data dependence described in reference to FIG. 11.Alternatively, the logic gate 474 could be replaced with other logicelements that achieve the same functionality.

[0066]FIG. 13 illustrates an example of a two-level 64 input MUX circuit500 suitable for use in the circuits discussed above. MUX circuit 500 isconstructed from a first level of 8-to-1 MUXes 502, 504, 506, 508, 510,512, 514 and 516 that are driven by most significant three bits of theCONTROL signal CONTROL<5:3>. The output of each of the first level MUXesis input to a second level 8-to-1 NMUX 520 that is driven by the nextthree least significant bits CONTROL<2:0>and a control bit <3>.

[0067] The output of 8-to-1 MUX 520 produces an output MUX_OUT for the64-input MUX circuit 500. According to an exemplary embodiment, any ofthe 64 inputs to the MUXes 502-516 can be selected to become the MUX OUTsignal. However, the 64 input signals are not just any digital signals.Instead, they correspond to 64 taps of the delay line. Therefore, asignal transition at a tap “0” may occur 50 pS before a signaltransition at a tap “1”, which then transitions 50 pS earlier that asignal at a tap “3”, and so on. This characteristic of the delay line,where every consecutive signal is delayed with respect to its firstneighboring signal, could change if the MUX adds more error than thisunit-delay spacing. To minimize the error introduced by the MUX, it isdesirable that the change between any two neighboring signals introducedby the MUX is identical.

[0068] For instance, the first eight taps of the delay line could beconnected to the first MUX 502, and the next eight taps could beconnected to the second MUX 504, and so on. In such an embodiment, ifthe MUX circuit 500 switches between a bit position 4 and a bit position5, then the only control signal that is changing is the control code onthe MUX 502, and the control code on the MUX 520 stays the same sincethe MUX 520 reads from the same MUX 502 in the two consecutive reads.Therefore, only one MUX is changing in between the bit positions 4 and5. However, in such a configuration, if the MUX circuit 500 switchesbetween bit positions 8 and 9 (i.e., a crossover point between the MUXes502 and 504), the control signals not only change on the input MUXes,but also on the output MUX 520, since the MUX 520 now selects the outputfrom the second MUX 504. Thus, the process of changing from the bitpositions 8 and 9 results in two changes rather than one change as inthe case of switching from the bit positions 4 and 5. Therefore, such aconfiguration is not desirable.

[0069] Instead, according to a preferred embodiment, the delay line tapsare wrapped around the eight MUXs 502-516 so that the control codechanges only once during any bit position read. The delay line taps areconnected to the MUXes in such a way so that the bit position 1 isconnected to the first input of the MUX 502, the bit position 2 isconnected to the first input of the MUX 504, the bit position 3 isconnected to the first input of the MUX 506, and so on until the bitposition 8 is connected to the first input of the MUX 516. According tothis embodiment, the next bit position, i.e., the bit position 9, isalso connected to the MUX 516. Specifically, the bit position 9 isconnected to the second input of the MUX 516. Similarly, going up theline of MUXes, the bit positions 10, 11, 12, 13, 14, and 15 areconnected to the second inputs of the MUXes 514, 512, 510, 508, 506, and504. Similarly to the bit positions 8 and 9 being connected to the sameMUX 516, the bit positions 16 and 17 are connected to the MUX 502. Insuch a setup, eight inputs to the MUX 502 are bit positions 1, 16, 17,32, 33, 48, 49, and 64.

[0070] Using the MUX setup described in the preceding paragraph, whenthe circuit 500 switches between bit positions 1 through 8, none of thecontrol signals on the MUXes 502-516 are changing, and only the controlsignal on the output MUX 520 is changing to select a different MUX foreach consecutive output. When the circuit crosses from the bit position8 to the bit position 9, the control signals to the MUxes 502-516 arechanging, but the control signal on the MUX 520 remains the same sincethe bit position 8 and the bit position 9 are read from the same MUX516. As the count increases from the bit position 3 to the bit position16, the MUX 520 moves up the line from the MUX 516 towards the MUX 502by changing the control signal being input to the MUX 520. In all cases,only one MUX changes in between any two consecutive positions.

[0071] As mentioned earlier, the MUXes 502-516 are driven by three mostsignificant bits of the control signal (i.e., CONTROL <5:3>), and thethree bits are decoded into one of eight values, and the decoded valueselects which input is passed to the MUX's output. For example, if thethree bits are “010”, then the second input is passed to the output.Similarly, the output MUX 520 is driven by three least significant bits,i.e., CONTROL <2:0>, and a control signal <3>. The extra control signalis used to invert the three least significant bits. If the controlsignal is low, no inversion is done, and bits “010” in CONTROL<2:0>indicate that the second input of the MUX 520 drives the MUX_OUT.If the control signal is high, then the bits “010” are inverted to“101”, and the fifth input is now selected. In such an embodiment, thecontrol code “000111” selects the eighth delay line position, and thecontrol word “001000” selects the ninth bit position.

[0072]FIG. 14 is a logic circuit diagram illustrating an embodiment ofan edge-triggered RS latch 550 suitable for use in the embodiments, e.g.as SR latch 130 of FIG. 1 and FIG. 7. The SR latch illustrated in FIG.14 has a transition delay of a set signal (S) to an output signal (Q)that is equal to a signal transition from a reset signal (R) to the Qsignal.

[0073] In the SR latch 550, a D flip-flop 552 is clocked by a signalreceived at the S input, which then clocks a logical one from VDD tooutput Q of the flip-flop 552. The output Q of the flip-flop 552 iscoupled to an input of a NOR gate 570 and further through an inverter556 to an input of a NAND gate 560. Similarly, a D flip-flop 554 isclocked by a signal received at the R input, which then clocks a logicalone from V_(DD) to an output Q of the flip-flop 554. An output Q of theflip-flop 554 is coupled to an input of a NOR gate 572 and through aninverter 558 to an input of a NAND gate 562. The NAND gates 560 and 562are cross-coupled such that the output of each is input to the other.Likewise, the NOR gates 570 and 572 are cross-coupled such that theoutput of each is input to the other. The output of the NAND gate 560drives an inverter 566 that, in turn, drives an output QB. The output ofthe NAND gate 562 drives an inverter 564 that, in turn, drives an outputQ. Similarly, the output of the NOR gate 570 drives an inverter 574that, in turn, drives the output Q. The output of the NOR gate 572drives an inverter 576 that, in turn, drives the output QB. The Q outputdrives an inverted reset input of the D flip-flop 554 and the QB outputdrives an inverted reset input of a D flip-flop 552. The NAND gates 560and 562 and the NOR gates 570 and 572 preserve the state of the outputsQ and QB of the RS latch 550, which are determined by the signals inputto the S and R inputs.

[0074] The wired OR produced by the coupling of the outputs of theinverters 564 and 574 and the interpolator such as the wired or producedby the coupling of the outputs of the inverters 566 and 576 accommodatesthe one gate delay difference introduced by the inverters 556 and 558.The number of gate delays from each of the S and R inputs to outputs Qand QB is approximately the same, which reduces the possibility of arace condition arising from signals arriving at different points of thecircuit at different times.

[0075] The foregoing circuit may be readily implemented by those skilledin the art of digital circuit design, and the embodiments described arenot intended to be limited to any particular process or fabricationtechniques. For instance, a conventional synthesized logic design flowmay be used. It should be understood that the present invention is notlimited to the circuits, methods and systems described herein.Equivalent circuits will become apparent to those skilled in the art ofcircuit design upon review of the foregoing. The performance of varioustypes of circuits and systems may be improved through the application ofthe teachings described herein.

[0076] In view of the wide variety of embodiments to which theprinciples of the present invention can be applied, it should beunderstood that the illustrated embodiments are examples only, andshould not be taken as limiting the scope of the present invention. Forexample, the circuits may employ different types of transistors andamplifiers to obtain the functions described above and the functions maybe achieved with more or fewer elements that those illustrated above.Further, some elements of the embodiments described may be implementedin software, hardware, firmware, or a combination of these approaches.Further, it will be apparent-to those of ordinary skill in the art thatthe teachings of the present invention may be applied to other systemsbesides RAMBUS based data busses.

[0077] The claims should not be read as limited to the described orderor elements unless stated to that effect. Therefore, all embodimentsthat come within the scope and spirit of the following claims andequivalents thereto are claimed as the invention.

What is claimed is:
 1. A circuit for selectively delaying a referenceclock signal, comprising: a phase splitter having a first output and asecond output; a first delay line having a set of output taps, the firstdelay line being coupled to the first output; a second delay line havinga set of output taps, the second delay line being coupled to the secondoutput; a first multiplexor coupled to the set of output taps from thefirst delay line, the first multiplexor providing an output that iscoupled to a first storage device; a second multiplexor coupled to theset of output taps from the second delay line, the second multiplexorproviding an output that is coupled to the first storage device; andmeans for comparing an output of the first storage device to an inputclock signal and generating a first control signal.
 2. A circuit ofclaim 1, wherein the first control signal is coupled to at least one ofthe first multiplexor and the second multiplexor.
 3. A circuit of claim1, wherein the comparing means comprises a first phase detector.
 4. Acircuit of claim 3, wherein the comparing means further comprises acontroller coupled to the first phase detector.
 5. A circuit of claim 4,wherein the controller generates control signals that are coupled to thefirst multiplexor and the second multiplexor.
 6. A circuit of claim 5,wherein the control signals cause the first multiplexor and the secondmultiplexor to select an output tap from the respective sets of outputtaps.
 7. A circuit of claim 1, further comprising: a third multiplexorcoupled to the set of output taps from the first delay line, the thirdmultiplexor providing an output that is coupled to a first interpolatorcircuit; a fourth multiplexor coupled to the set of output taps from thesecond delay line, the fourth multiplexor providing an output that iscoupled to the first interpolator circuit; a fifth multiplexor coupledto the set of output taps from the first delay line, the fifthmultiplexor providing an output that is coupled to a second interpolatorcircuit; a sixth multiplexor coupled to the set of output taps from thesecond delay line, the sixth multiplexor providing an output that iscoupled to the second interpolator circuit; the first interpolatorproviding an output that is coupled to a second storage device; thesecond interpolator providing an output that is coupled to the secondthe second storage device; the second storage device providing an outputthat provides a quadrature output clock signal; and a quadrature controlcircuit for generating control signals that are coupled to the thirdmultiplexor, the fourth multiplexor, the fifth multiplexor, and thesixth multiplexor.
 8. A circuit of claim 7, wherein the control signalsgenerated at the quadrature control circuit cause the third multiplexor,the fourth multiplexor, the fifth multiplexor, and the sixth multiplexorto select an output tap from the respective sets of output taps.
 9. Acircuit of claim 7, further comprising a phase detector being coupled tothe output of the third multiplexor and the output of the fourthmultiplexor, the phase detector providing an output that is coupled tothe quadrature control circuit.
 10. A circuit of claim 9, wherein thequadrature control circuit is further coupled to the first controlsignal.
 11. A circuit of claim 1, wherein the first delay line includesa power control input for receiving a power control signal, wherein thefirst delay line is further configured to power down selected elementsof the first delay line responsive to the power control signal; thesecond delay line further includes a power control input for receivingthe power control signal, wherein the second delay line is furtherconfigured to power down selected elements of the second delay lineresponsive to the power control signal; and the control circuit includesa power control output for generating the power control signal, whereinthe control circuit is further configured to generate the power controlsignal based upon the first control signal such that unnecessary delayelements in the first and second delay line are disabled.
 12. A circuitof claim 11, further comprising means for detecting a cycle boundary ofthe reference clock signal and for generating a cycle boundary signal.13. A circuit of claim 12, wherein the cycle boundary signal is coupledto means for generating the first control signal and the power controlsignal.
 14. A circuit of claim 1, wherein each multiplexor comprises aplurality of first level multiplexors coupled to respective output taps,wherein each first level multiplexor generates an output coupled to asecond level multiplexor, wherein each first level multiplexor includesa control input for receiving a first control word derived from thefirst control signal, wherein the second level multiplexor includes acontrol input for receiving a second control word derived from the firstcontrol signal, and wherein the plurality of first level multiplexorsare connected to the respective sets of output taps such that only oneof the first control word and the second control word is changingbetween switching from one output tap position to a next output tapposition.
 15. The circuit of claim 14, wherein the output taps compriseat least a first plurality of output taps and a second plurality ofoutput taps, and wherein each consecutive tap of the first plurality ofoutput taps is connected to first inputs of each consecutive multiplexorof the plurality of first level multiplexors starting with a firstmultiplexor until the last multiplexor is reached, and wherein eachconsecutive tap of the second plurality of output taps is connected tosecond inputs of each consecutive multiplexor starting with the lastmultiplexor of the plurality of first level multiplexor until the firstmultiplexor is reached.
 16. A circuit for selectively delaying areference clock signal, the circuit comprising: a phase splitter forreceiving a reference clock signal and outputting an in-phase referencesignal and a complementary reference signal, where the complementaryreference signal is complementary to the in-phase reference signal; afirst delay line having an input for receiving the in-phase referencesignal and a set of output taps for outputting the in-phase referencesignal with successively increasing delay; a first multiplexor (MUX)having a plurality of inputs, each one of the plurality of inputs beingcoupled to a corresponding one of the set of output taps of the firstdelay line, the first MUX having a control input for receiving a firstcontrol signal for selecting one of the plurality of inputs for couplingto an output of the first MUX; a second delay line having an input forreceiving the complementary reference signal and a set of output tapsfor outputting the complementary reference signal with successivelyincreasing delay; a second MUX having a plurality of inputs, each one ofthe plurality of inputs being coupled to a corresponding one of the setof output taps of the second delay line, the second MUX having a controlinput for receiving the first control signal for selecting one of theplurality of inputs for coupling to an output of the second MUX; a firstlatch having a set input coupled to the output of the first MUX, a resetinput coupled to the output of the second MUX, and an output forproducing an output clock signal; a phase detector having a first inputfor receiving a feedback clock signal corresponding to the output clocksignal, a-second input for receiving an input clock signal, where thephase detector is configured to output a difference signal at an outputof the phase detector that indicates a phase relationship between thefeedback clock signal and the input clock signal; and a controllerhaving an input for receiving the difference signal and an output forgenerating the first control signal, where the controller is configuredto adjust the control signal responsive to the difference signal so asto align the feedback clock signal and the input clock signal.
 17. Thecircuit of claim 16, the circuit further comprising: a third MUX havinga plurality of inputs, each one of the plurality of inputs being coupledto a corresponding one of the set of output taps of the first delayline, the third MUX having a control input for receiving a secondcontrol signal for selecting one of the plurality of inputs for couplingto an output of the third MUX, wherein the third MUX outputs a delayedversion of the selected input from the first delay line; a fourth MUXhaving a plurality of inputs, each one of the plurality of inputs beingcoupled to a corresponding one of the set of output taps of the seconddelay line, the fourth MUX having a control input for receiving a thirdcontrol signal for selecting one of the plurality of inputs for couplingto an output of the fourth MUX, wherein the fourth MUX outputs anadvanced version of the selected input from the second delay line; afirst interpolator circuit having a first input coupled to the output ofthe third MUX, and having a second input coupled to the output of thefourth MUX, and an output for generating a first quadrature signal; afifth MUX having a plurality of inputs, each one of the plurality ofinputs being coupled to a corresponding one of the set of output taps ofthe first delay line, the fifth MUX having a control input for receivinga fourth control signal for selecting one of the plurality of inputs forcoupling to an output of the fifth MUX, wherein the fifth MUX outputs anadvanced version of the selected input from the first delay line; asixth MUX having a plurality of inputs, each one of the plurality ofinputs being coupled to a corresponding one of the set of output taps ofthe second delay line, the sixth MUX having a control input forreceiving a fifth control signal for selecting one of the plurality ofinputs for coupling to an output of the sixth MUX, wherein the sixth MUXoutputs a delayed version of the selected input from the second delayline; a second interpolator circuit having a first input coupled to theoutput of the fifth MUX, a second input coupled to the output of thesixth MUX, and an output for generating a second quadrature signal; asecond latch having a set input coupled to the output of the firstinterpolator, a reset input coupled to the output of the secondinterpolator, and an output for producing a quadrature output clocksignal; a first flip-flop having a data input coupled to the output ofthe fourth MUX, a clock input coupled to the output of the third MUX,and a data output for generating a first test signal; and a quadraturecontrol circuit having a first input for receiving the first controlsignal, a second input coupled to the data output of the firstflip-flop, a first output for generating the second control signal, asecond output for generating the third control signal, a third outputfor generating the fourth control signal, and a fourth output forgenerating a fifth control signal, where the quadrature control circuitgenerates the second control signal and the fifth control signal byoffsetting the first control signal by a selected offset value in afirst direction relative to the magnitude of the first control signaland generates the third control signal and the fourth control signal byoffsetting the first control signal by the selected offset value in asecond direction that is opposite to the first direction, where theselected offset value is selected by starting with a first value andsuccessively changing the selected offset value until the test signalchanges value.
 18. The circuit of claim 17, where the quadrature controlcircuit is further configured to start with a first minimum value forthe offset value, and successively increment the selected offset valueuntil the test signal changes value and then decrement the selectedoffset value.
 19. The circuit of claim 17, where the quadrature controlcircuit is further configured to start with a maximum value for theoffset value and successively decrement the selected offset value untilthe test signal changes value.
 20. The circuit of claim 17, where thequadrature control circuit is integrated with the control circuit. 21.The circuit of claim 17, where the first interpolator circuit furthercomprises: a first inverter having an input coupled to the output of thethird MUX and an output; a second inverter having an input coupled tothe output of the fourth MUX and an output; and a third inverter havingan input coupled to the outputs of the first and second inverters and anoutput for generating the first quadrature signal, where the thirdinverter is a relatively larger device than first and second inverterdevices, and wherein the first quadrature signal is a 90-degree signalrelative to the output clock signal.
 22. The circuit of claim 17,wherein the second interpolator circuit further comprises: a fourthinverter having an input coupled to the output of the fifth MUX and anoutput; a fifth inverter having an input coupled to the output of thesixth MUX and an output; and a sixth inverter having an input coupled tothe outputs of the fourth and fifth inverters and an output forgenerating the second quadrature signal, where the sixth inverter is arelatively larger device than the fourth and fifth inverter devices, andwherein the second quadrature signal is 270-degree signal relative tothe output clock signal.
 23. The circuit of claim 16, wherein: the firstdelay line further includes a power control input for receiving a powercontrol signal, where the first delay line is further configured topower down selected elements of the first delay line responsive to thepower control signal; the second delay line further includes a powercontrol input for receiving the power control signal, where the seconddelay line is further configured to power down selected elements of thesecond delay line responsive to the power control signal; and thecontrol circuit includes a power control output for generating the powercontrol signal, where the control circuit is-further configured togenerate the power control signal based upon the first control signalsuch that unnecessary delay elements in the first and second delay linesare disabled.
 24. The circuit of claim 16, where the reference clocksignal and input clock signal are both configured to have a 50% dutycycle.
 25. The circuit of claim 16, further comprising means fordetecting a cycle boundary of the reference clock signal and forgenerating a cycle boundary signal.
 26. The circuit of claim 25, whereinthe cycle boundary signal is coupled to the controller generating thefirst control signal, and wherein the controller uses the cycle boundarysignal to adjust the first control signal.
 27. The circuit of claim 16,wherein each MUX comprises a plurality of first level multiplexorscoupled to respective output taps, wherein each first level multiplexorgenerates an output coupled to a second level multiplexor, wherein eachfirst level multiplexor includes a control input for receiving a firstcontrol word derived from the control signal, wherein the second levelmultiplexor includes a control input for receiving a second control wordderived from the control signal, and wherein the first level ofmultiplexors are connected to the respective sets of output taps suchthat only one of the first control word and the second control word ischanging between switching from one output tap position to a next outputtap position.
 27. A method for recovering a clock signal from an inputclock signal, comprising the steps of: converting a reference clocksignal into an in-phase reference signal and a complementary referencesignal; delaying the in-phase reference signal and the complementaryreference signal; generating an output clock signal from the delayedin-phase reference signal and the complementary reference signal;comparing a feedback signal representing the output clock signal to theinput clock signal to generate a first control signal; and adjusting alength of delay for at least one of the in-phase reference signal andthe complementary reference signal based upon the control signal. 28.The method of claim 27, further comprising: comparing the delayedin-phase reference signal and the delayed complementary reference clocksignal to generate a test signal; generating a set of quadrature controlsignals using the test signal and the first control signal; selectingthe delayed in-phase reference signal and the delayed complementaryreference clock signal based on the set of quadrature control signals togenerate a first set of signals and a second set of signals;interpolating between the first set signal to generate a firstquadrature signal; interpolating between the second set of signals togenerate a second quadrature signal; and generating a quadrature clocksignal using the first quadrature signal and the second quadraturesignal.
 29. The method of claim 27, wherein delaying the in-phasereference signal and the complementary reference signal comprisesdelaying the in-phase reference signal and the complementary referencesignal via at least two delay lines, and wherein the method furthercomprises: generating a power control signal for powering down selectedelements of the at least two delay lines.
 30. The method of claim 29,further comprising: generating a cycle boundary signal for adjusting thepower control signal and the control signal.
 31. A method for recoveringa clock signal from an input clock signal, the method comprising thesteps of: converting a reference clock signal into an in-phase referencesignal and a complementary reference signal; successively delaying thein-phase reference clock signal to produce a series of delayed in-phasereference clock signals; successively delaying the complementaryreference clock signal to produce a series of delayed complementaryreference clock signals; selecting a first one of the series of delayedin-phase reference clock signals and a first one of the series ofdelayed complementary reference clock signals responsive to a firstcontrol signal, where the first one of the series of delayedcomplementary reference clock signals corresponds to the first one ofthe series of delayed in-phase reference clock signals; generating anoutput clock signal by producing a rising edge in the output clocksignal responsive to a rising edge in the first one of the series ofdelayed in-phase reference clock signals and producing a falling edge inthe output clock signal responsive to a rising edge in the first one ofthe series of delayed complementary reference clock signals; receivingthe input clock signal; comparing the input clock signal to a feedbackclock signal related to the output clock signal to produce a differencesignal; and generating the first control signal responsive to thedifference signal in order to bring the feedback clock signal into phasewith the input clock signal.
 32. The method of claim 31, furthercomprising generating the reference clock signal to have a correct dutycycle.
 33. The method of claim 31, the method further comprising thesteps of: selecting a second one of the series of delayed in-phasereference clock signals responsive to a second control signal; selectinga second one of the series of delayed complementary reference clocksignals responsive to a third control signal; selecting a third one ofthe series of delayed in-phase reference clock signals responsive to afourth control signal; selecting a fourth one of the series of delayedcomplementary reference clock signals responsive to a fifth controlsignal; sensing a phase relationship between the second one of theseries of delayed in-phase reference clock signals and the second one ofthe series of delayed complementary reference clock signals to produce atest signal; generating the second, third, fourth and fifth controlsignals based upon the first control signal and adjusting the second,third, fourth, and fifth control signals until a state change isdetected in the test signal; interpolating between the second one-of theseries of delayed in-phase reference clock signals and the second one ofthe series of delayed complementary reference clock signals to produce afirst quadrature signal; interpolating between the third one of theseries of delayed in-phase reference clock signals and the third one ofthe series of delayed complementary reference clock signals to produce asecond quadrature signal; and generating a quadrature output clocksignal using the first quadrature signal and the second quadraturesignal.
 34. The method of claim 33, where the step of generating thesecond, third, fourth, and fifth control signals based upon the firstcontrol signal and adjusting the second, third, fourth, and fifthcontrol signals until a state change is detected in the test signalfurther comprises the steps of: generating the second control signal byoffsetting the first control signal value by an offset value in a firstdirection relative to the magnitude of the first control signal;generating the third control signal by offsetting the first controlsignal value by the offset value in a second direction relative to themagnitude of the first control signal; selecting a first value for theoffset value; and successively changing the offset value until the statechange is detected in the test signal.
 35. The method of claim 34,where: the step of selecting a first value for the offset value furthercomprises selecting a minimum value for the offset value; and the stepof successively changing the offset value until the state change isdetected in the test signal further comprises successively incrementingthe offset value until the state change is detected in the test signaland then decrementing the offset value.
 36. The method of claim 34,where: the step of selecting a first value for the offset value furthercomprises selecting a maximum value for the offset value; and the stepof successively changing the offset value until the state change isdetected in the test signal further comprises successively decrementingthe offset value until the state change is detected in the test signal.37. The method of claim 33, where the step of interpolating between thesecond one of the series of delayed in-phase reference clock signals andthe second one of the series of delayed complementary reference clocksignals to produce a first quadrature signal further comprises the stepsof: driving an input of a first large driver device with a first smalldriver device responsive to the second one of the series of delayedin-phase reference clock signals; and driving the input of the firstlarge driver device with a second small driver device responsive to thesecond one of the series of delayed complementary reference clocksignals.
 38. The method of claim 33, wherein the step of interpolatingbetween the third one of the series of the delayed in-phase referenceclock signal and the third one of the series of delayed complementaryreference clock signals to produce a second quadrature signal furthercomprises the steps of: driving an input of a second larger driverdevice with a third small driver device responsive to the third one ofthe series of delayed in-phase reference clock signals; and driving theinput of the second larger driver device with a fourth small driverdevice responsive to the third one of the series of delayedcomplementary reference clock signals.
 39. The method of claim 33, wherethe step of sensing a phase relationship between the second one of theseries of delayed in-phase reference clock signals and the second one ofthe series of delayed complementary reference clock signals responsiveto a third control signal to produce a test signal further comprisesclocking the second one of the series of delayed complementary referenceclock signals with the second one of the series of delayed in-phasereference clock signals to obtain the test signal.
 40. The method ofclaim 34, where: the step of successively delaying the in-phasereference clock signal to produce a series of delayed in-phase referenceclock signals further comprises delaying the in-phase reference signalwith a first series of delay elements to produce the series of delayedin-phase reference clock signals; the step of successively delaying thecomplementary reference clock signal to produce a series of delayedcomplementary reference clock signals further comprises delaying thecomplementary reference clock signal with a second series of delayelements to produce the series of delayed complementary reference clocksignals; and the method includes the step of disabling unused ones ofthe first and second series of delay elements.
 41. The method of claim31, where the step of generating a reference clock signal having acorrect duty cycle further comprises generating the reference clocksignal with a 50% duty cycle.
 42. An apparatus for recovering an inputclock signal, the apparatus comprising: means for generating a referenceclock signal having a correct duty cycle; means for converting thereference clock signal into an in-phase reference signal and acomplementary reference signal; means for successively delaying thein-phase reference clock signal to produce a series of delayed in-phasereference clock signals; means for successively delaying thecomplementary reference clock signal to produce a series of delayedcomplementary reference clock signals; means for selecting a first oneof the series of delayed in-phase reference clock signals and a firstone of the series of delayed complementary reference clock signalsresponsive to a first control signal, where the first one of the seriesof delayed complementary reference clock signals corresponds to thefirst one of the series of delayed in-phase reference clock signals;means for generating an output clock signal by producing a rising edgein the output clock signal responsive to a rising edge in the first oneof the series of delayed in-phase reference clock signals and producinga falling edge in the output clock signal responsive to a rising edge inthe first one of the series of delayed complementary reference clocksignals; means for receiving the input clock signal; means for comparingthe input clock signal to a feedback clock signal related to the outputclock signal to produce a difference signal; and means for generatingthe first control signal responsive to the difference signal in order tobring the feedback clock signal into phase with the input clock signal.43. The apparatus of claim 42, the apparatus further including: meansfor selecting a second one of the series of delayed in-phase referenceclock signals responsive to a second control signal; means for selectinga second one of the series of delayed complementary reference clocksignals responsive to a third control signal; means for sensing a phaserelationship between the second one of the series of delayed in-phasereference clock signals and the second one of the series of delayedcomplementary reference clock signals responsive to the first controlsignal to produce a test signal; means for selecting a third one of theseries of delayed in-phase reference clock signals responsive to afourth control signal; means for selecting a third one of the series ofdelayed complementary reference clock signals responsive to a fifthcontrol signal; means for generating the second, third, fourth and fifthcontrol signals based upon the first control signal and adjusting thesecond and third control signals until a state change is detected in thetest signal; means for interpolating between the second one of theseries of delayed in-phase reference clock signals and the second one ofthe series of delayed complementary reference clock signals to produce afirst quadrature signal; means for interpolating between the third oneof the series of delayed in-phase references clock signals and the thirdone of the series of delayed complementary reference clock signals toproduce a second quadrature signal; and means for producing a quadratureoutput clock signal using the first quadrature signal and the secondquadrature signal.
 44. The apparatus of claim 43, where the means forgenerating the second, third, fourth, and fifth control signals basedupon the first control signal and adjusting the second and third controlsignals until a state change is detected in the test signal furthercomprises: means for generating the second control signal and the fifthcontrol signal by offsetting the first control signal value by an offsetvalue in a first direction relative to the magnitude of the firstcontrol signal; means for generating the third control signal and thefourth control signal by offsetting the first control signal value bythe offset value in a second direction relative to the magnitude of thefirst control signal; means for selecting a first value for the offsetvalue; and means for successively changing the offset value until thestate change is detected in the test signal.
 45. The apparatus of claim44, where: the means for selecting a first value for the offset valuefurther comprises means selecting a minimum value for the offset value;and the means for successively changing the offset value until the statechange is detected in the test signal further comprises means forsuccessively incrementing the offset value until the state change isdetected in the test signal and then decrementing the offset value; andthe step of selecting a first value for the offset value furthercomprises selecting a maximum value for the offset value; and the stepof successively changing the offset value until the state change isdetected in the test signal further comprises successively decrementingthe offset value until the state change is detected in the test signal.46. The apparatus of claim 43, where the means for interpolating betweenthe second one of the series of delayed in-phase reference clock signalsand the second one of the series of delayed complementary referenceclock signals to produce a first quadrature signal further comprises:means for driving an input of a first large driver device with a firstsmall driver device responsive to the second one of the series ofdelayed in-phase reference clock signals; and means for driving theinput of the first large driver device with a second small driver deviceresponsive to the second one of the series of delayed complementaryreference clock signals.
 47. The apparatus of claim 43, where the meansfor interpolating between the third one of the series of delayedin-phase references clock signals and the third one of the series ofdelayed complementary reference clock signals to produce a secondquadrature signal further comprises: means for driving an input of asecond large driver device with a third small driver device responsiveto the third one of the series of delayed in-phase reference clocksignals; and means for driving the input of the second larger driverdevice with a fourth small driver device responsive to the third one ofthe series of delayed complementary reference clock signals.
 48. Theapparatus of claim 43, where the means for sensing a phase relationshipbetween the second one of the series of delayed in-phase reference clocksignals and the second one of the series of delayed complementaryreference clock signals responsive to a third control signal to producea test signal further comprises means for clocking the second one of theseries of delayed complementary reference clock signals with the secondone of the series of delayed in-phase reference clock signals to obtainthe test signal.
 49. The apparatus of claim 42, where: the means forsuccessively delaying the in-phase reference clock signal to produce aseries of delayed in-phase reference clock signals further comprisesmeans for delaying the in-phase reference signal with a first series ofdelay elements to produce the series of delayed in-phase reference clocksignals; the means for successively delaying the complementary referenceclock signal to produce a series of delayed complementary referenceclock signals further comprises means for delaying the complementaryreference clock signal with a second series of delay elements to producethe series of delayed complementary reference clock signals; and theapparatus includes means for disabling unused ones of the first andsecond series of delay elements.
 50. The apparatus of claim 42, wherethe means for generating a reference clock signal having a correct dutycycle further comprises means for generating the reference clock signalwith a 50% duty cycle.
 51. The apparatus of claim 42, further comprisingmeans for detecting a cycle boundary of the reference clock signal togenerate a cycle boundary signal.